WIDEBUS=STANDARD_BUS_MODE_O, ENABLE=CLOCK_DISABLED_, PWRSAVE=ALWAYS_ENABLED_, BYPASS=DISABLE_BYPASS_
Clock control register.
| CLKDIV | Bus clock period: SD_CLK frequency = MCLK / [2x(ClkDiv+1)]. |
| ENABLE | Enable SD card bus clock: 0 (CLOCK_DISABLED_): Clock disabled. 1 (CLOCK_ENABLED_): Clock enabled. |
| PWRSAVE | Disable SD_CLK output when bus is idle: 0 (ALWAYS_ENABLED_): Always enabled. 1 (CLOCK_ENABLED_WHEN_B): Clock enabled when bus is active. |
| BYPASS | Enable bypass of clock divide logic: 0 (DISABLE_BYPASS_): Disable bypass. 1 (ENABLE_BYPASS_MCLK_): Enable bypass. MCLK driven to card bus output (SD_CLK). |
| WIDEBUS | Enable wide bus mode. 0 (STANDARD_BUS_MODE_O): Standard bus mode (only SD_DAT[0] used). 1 (WIDE_BUS_MODE_SD_DA): Wide bus mode (SD_DAT[3:0] used) |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |